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Rev Log message Author Age Path
65 RAM_BE system verilog version unneback 4738d 09h /
64 SPR reset value unneback 4738d 09h /
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4738d 09h /
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4738d 10h /
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4738d 10h /
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4740d 05h /
59 added WB RAM B3 with byte enable unneback 4741d 05h /
58 corrected EXT unit, rewrite of FF1, FL1 unneback 4757d 12h /
57 corrected EXT unit, rewrite of FF1, FL1 unneback 4757d 12h /
56 WB B4 RAM we fix unneback 4770d 05h /
55 added WB_B4RAM with byte enable unneback 4772d 11h /
54 added WB_B4RAM with byte enable unneback 4772d 11h /
53 added WB_B4RAM with byte enable unneback 4772d 11h /
52 added WB_B4RAM with byte enable unneback 4772d 11h /
51 added WB_B4RAM with byte enable unneback 4772d 12h /
50 added WB_B4RAM with byte enable unneback 4772d 12h /
49 added WB_B4RAM with byte enable unneback 4772d 12h /
48 wb updated unneback 4779d 06h /
47 added help program for LFSR counters unneback 4874d 09h /
46 updated parity unneback 4875d 10h /
45 updated timing in io models unneback 4877d 05h /
44 added target independet IO functionns unneback 4880d 04h /
43 added logic for parity generation and check unneback 4884d 08h /
42 updated mux_andor unneback 4888d 08h /
41 typo in registers.v unneback 4888d 09h /
40 new build environment with custom.v added as a result file unneback 4888d 09h /
39 added simple port prio based wb arbiter unneback 4889d 06h /
38 updated andor mux unneback 4889d 06h /
37 corrected polynom with length 20 unneback 4895d 03h /
36 added generic andor_mux unneback 4896d 11h /

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