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[/] [versatile_library/] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 5329d 10h /versatile_library
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5329d 11h /versatile_library
25 added sync FIFO unneback 5330d 01h /versatile_library
24 added vl_dff_ce_set unneback 5331d 08h /versatile_library
23 fixed port map error in async fifo 1r1w unneback 5331d 23h /versatile_library
22 added binary counters unneback 5332d 04h /versatile_library
21 reg -> wire in and or mux in logic unneback 5333d 00h /versatile_library
20 naming convention vl_ unneback 5334d 11h /versatile_library
19 naming convention vl_ unneback 5334d 11h /versatile_library
18 naming convention vl_ unneback 5334d 12h /versatile_library
17 unneback 5398d 01h /versatile_library
16 converting utility for ROM unneback 5398d 12h /versatile_library
15 added delay line unneback 5404d 09h /versatile_library
14 reg -> wire for various signals unneback 5404d 14h /versatile_library
13 cosmetic update unneback 5404d 15h /versatile_library
12 added wishbone comliant modules unneback 5405d 11h /versatile_library
11 async fifo simplex unneback 5406d 02h /versatile_library
10 added dff_ce_clear unneback 5408d 01h /versatile_library
9 added dff_ce_clear unneback 5408d 01h /versatile_library
8 added dff_ce_clear unneback 5408d 01h /versatile_library
7 mem update unneback 5408d 02h /versatile_library
6 added library files unneback 5421d 02h /versatile_library
5 memories added unneback 5421d 03h /versatile_library
4 added counters unneback 5425d 07h /versatile_library
3 various updates
counter added		 unneback 5428d 02h /versatile_library
2 initial check-in unneback 5429d 02h /versatile_library
1 The project and the structure was created root 5434d 07h /versatile_library

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