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[/] [versatile_library/] - Rev 28

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Rev Log message Author Age Path
28 added sync simplex FIFO unneback 4938d 10h /versatile_library/
27 added sync simplex FIFO unneback 4938d 10h /versatile_library/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4938d 11h /versatile_library/
25 added sync FIFO unneback 4939d 01h /versatile_library/
24 added vl_dff_ce_set unneback 4940d 08h /versatile_library/
23 fixed port map error in async fifo 1r1w unneback 4940d 23h /versatile_library/
22 added binary counters unneback 4941d 04h /versatile_library/
21 reg -> wire in and or mux in logic unneback 4942d 00h /versatile_library/
20 naming convention vl_ unneback 4943d 11h /versatile_library/
19 naming convention vl_ unneback 4943d 11h /versatile_library/
18 naming convention vl_ unneback 4943d 11h /versatile_library/
17 unneback 5007d 01h /versatile_library/
16 converting utility for ROM unneback 5007d 12h /versatile_library/
15 added delay line unneback 5013d 08h /versatile_library/
14 reg -> wire for various signals unneback 5013d 14h /versatile_library/
13 cosmetic update unneback 5013d 15h /versatile_library/
12 added wishbone comliant modules unneback 5014d 11h /versatile_library/
11 async fifo simplex unneback 5015d 02h /versatile_library/
10 added dff_ce_clear unneback 5017d 01h /versatile_library/
9 added dff_ce_clear unneback 5017d 01h /versatile_library/
8 added dff_ce_clear unneback 5017d 01h /versatile_library/
7 mem update unneback 5017d 02h /versatile_library/
6 added library files unneback 5030d 02h /versatile_library/
5 memories added unneback 5030d 03h /versatile_library/
4 added counters unneback 5034d 06h /versatile_library/
3 various updates
counter added
unneback 5037d 02h /versatile_library/
2 initial check-in unneback 5038d 02h /versatile_library/
1 The project and the structure was created root 5043d 06h /versatile_library/

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