OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] - Rev 69

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
69 no arbiter in wb_b3_ram_be unneback 4656d 15h /versatile_library/
68 ram_be updated to optional mem_size unneback 4656d 15h /versatile_library/
67 support up to 8 wbm on arbiter unneback 4657d 14h /versatile_library/
66 RAM_BE ack_o vector unneback 4695d 13h /versatile_library/
65 RAM_BE system verilog version unneback 4695d 14h /versatile_library/
64 SPR reset value unneback 4695d 14h /versatile_library/
63 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4695d 15h /versatile_library/
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4695d 15h /versatile_library/
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4695d 15h /versatile_library/
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4697d 10h /versatile_library/
59 added WB RAM B3 with byte enable unneback 4698d 11h /versatile_library/
58 corrected EXT unit, rewrite of FF1, FL1 unneback 4714d 17h /versatile_library/
57 corrected EXT unit, rewrite of FF1, FL1 unneback 4714d 17h /versatile_library/
56 WB B4 RAM we fix unneback 4727d 10h /versatile_library/
55 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
54 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
53 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
52 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
51 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
50 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
49 added WB_B4RAM with byte enable unneback 4729d 17h /versatile_library/
48 wb updated unneback 4736d 11h /versatile_library/
47 added help program for LFSR counters unneback 4831d 14h /versatile_library/
46 updated parity unneback 4832d 16h /versatile_library/
45 updated timing in io models unneback 4834d 10h /versatile_library/
44 added target independet IO functionns unneback 4837d 10h /versatile_library/
43 added logic for parity generation and check unneback 4841d 13h /versatile_library/
42 updated mux_andor unneback 4845d 13h /versatile_library/
41 typo in registers.v unneback 4845d 14h /versatile_library/
40 new build environment with custom.v added as a result file unneback 4845d 15h /versatile_library/

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.