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[/] [versatile_library/] [trunk/] [rtl/] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 4426d 09h /versatile_library/trunk/rtl/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4426d 11h /versatile_library/trunk/rtl/
25 added sync FIFO unneback 4427d 00h /versatile_library/trunk/rtl/
24 added vl_dff_ce_set unneback 4428d 08h /versatile_library/trunk/rtl/
23 fixed port map error in async fifo 1r1w unneback 4428d 23h /versatile_library/trunk/rtl/
22 added binary counters unneback 4429d 04h /versatile_library/trunk/rtl/
21 reg -> wire in and or mux in logic unneback 4430d 00h /versatile_library/trunk/rtl/
18 naming convention vl_ unneback 4431d 11h /versatile_library/trunk/rtl/
17 unneback 4495d 00h /versatile_library/trunk/rtl/
15 added delay line unneback 4501d 08h /versatile_library/trunk/rtl/
14 reg -> wire for various signals unneback 4501d 13h /versatile_library/trunk/rtl/
13 cosmetic update unneback 4501d 15h /versatile_library/trunk/rtl/
12 added wishbone comliant modules unneback 4502d 11h /versatile_library/trunk/rtl/
11 async fifo simplex unneback 4503d 02h /versatile_library/trunk/rtl/
10 added dff_ce_clear unneback 4505d 01h /versatile_library/trunk/rtl/
8 added dff_ce_clear unneback 4505d 01h /versatile_library/trunk/rtl/
7 mem update unneback 4505d 02h /versatile_library/trunk/rtl/
6 added library files unneback 4518d 02h /versatile_library/trunk/rtl/
5 memories added unneback 4518d 02h /versatile_library/trunk/rtl/
4 added counters unneback 4522d 06h /versatile_library/trunk/rtl/

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