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[/] [versatile_library/] [trunk/] [rtl/] - Rev 30

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Rev Log message Author Age Path
30 updated counter for level1 and level2 function unneback 4433d 15h /versatile_library/trunk/rtl/
29 updated counter for level1 and level2 function unneback 4433d 15h /versatile_library/trunk/rtl/
28 added sync simplex FIFO unneback 4434d 16h /versatile_library/trunk/rtl/
27 added sync simplex FIFO unneback 4434d 16h /versatile_library/trunk/rtl/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4434d 18h /versatile_library/trunk/rtl/
25 added sync FIFO unneback 4435d 07h /versatile_library/trunk/rtl/
24 added vl_dff_ce_set unneback 4436d 15h /versatile_library/trunk/rtl/
23 fixed port map error in async fifo 1r1w unneback 4437d 06h /versatile_library/trunk/rtl/
22 added binary counters unneback 4437d 11h /versatile_library/trunk/rtl/
21 reg -> wire in and or mux in logic unneback 4438d 07h /versatile_library/trunk/rtl/
18 naming convention vl_ unneback 4439d 18h /versatile_library/trunk/rtl/
17 unneback 4503d 07h /versatile_library/trunk/rtl/
15 added delay line unneback 4509d 15h /versatile_library/trunk/rtl/
14 reg -> wire for various signals unneback 4509d 20h /versatile_library/trunk/rtl/
13 cosmetic update unneback 4509d 22h /versatile_library/trunk/rtl/
12 added wishbone comliant modules unneback 4510d 18h /versatile_library/trunk/rtl/
11 async fifo simplex unneback 4511d 09h /versatile_library/trunk/rtl/
10 added dff_ce_clear unneback 4513d 08h /versatile_library/trunk/rtl/
8 added dff_ce_clear unneback 4513d 08h /versatile_library/trunk/rtl/
7 mem update unneback 4513d 09h /versatile_library/trunk/rtl/

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