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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 14

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Rev Log message Author Age Path
14 reg -> wire for various signals unneback 3764d 06h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3764d 08h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3765d 04h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3765d 18h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 3767d 17h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 3767d 17h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 3767d 18h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 3780d 19h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 3780d 19h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 3784d 23h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added
unneback 3787d 18h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 3788d 19h /versatile_library/trunk/rtl/verilog/

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