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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 27

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Rev Log message Author Age Path
27 added sync simplex FIFO unneback 5027d 23h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5028d 01h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 5028d 14h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 5029d 22h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 5030d 13h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 5030d 18h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 5031d 14h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 5033d 01h /versatile_library/trunk/rtl/verilog/
17 unneback 5096d 14h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 5102d 22h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 5103d 03h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 5103d 05h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 5104d 01h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 5104d 16h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 5106d 14h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 5106d 15h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 5106d 15h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 5119d 16h /versatile_library/trunk/rtl/verilog/
5 memories added unneback 5119d 16h /versatile_library/trunk/rtl/verilog/
4 added counters unneback 5123d 20h /versatile_library/trunk/rtl/verilog/
3 various updates
counter added		 unneback 5126d 15h /versatile_library/trunk/rtl/verilog/
2 initial check-in unneback 5127d 16h /versatile_library/trunk/rtl/verilog/

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