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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 29

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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 3688d 00h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 3689d 02h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 3689d 02h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3689d 03h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 3689d 16h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3691d 00h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3691d 15h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3691d 20h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3692d 16h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3694d 03h /versatile_library/trunk/rtl/verilog/
17 unneback 3757d 17h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3764d 00h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3764d 05h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3764d 07h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3765d 03h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3765d 18h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 3767d 17h /versatile_library/trunk/rtl/verilog/
8 added dff_ce_clear unneback 3767d 17h /versatile_library/trunk/rtl/verilog/
7 mem update unneback 3767d 18h /versatile_library/trunk/rtl/verilog/
6 added library files unneback 3780d 18h /versatile_library/trunk/rtl/verilog/

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