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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 29

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Rev Log message Author Age Path
29 updated counter for level1 and level2 function unneback 4911d 13h /versatile_library/trunk/rtl/verilog
28 added sync simplex FIFO unneback 4912d 14h /versatile_library/trunk/rtl/verilog
27 added sync simplex FIFO unneback 4912d 14h /versatile_library/trunk/rtl/verilog
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4912d 16h /versatile_library/trunk/rtl/verilog
25 added sync FIFO unneback 4913d 05h /versatile_library/trunk/rtl/verilog
24 added vl_dff_ce_set unneback 4914d 13h /versatile_library/trunk/rtl/verilog
23 fixed port map error in async fifo 1r1w unneback 4915d 04h /versatile_library/trunk/rtl/verilog
22 added binary counters unneback 4915d 09h /versatile_library/trunk/rtl/verilog
21 reg -> wire in and or mux in logic unneback 4916d 05h /versatile_library/trunk/rtl/verilog
18 naming convention vl_ unneback 4917d 16h /versatile_library/trunk/rtl/verilog
17 unneback 4981d 05h /versatile_library/trunk/rtl/verilog
15 added delay line unneback 4987d 13h /versatile_library/trunk/rtl/verilog
14 reg -> wire for various signals unneback 4987d 18h /versatile_library/trunk/rtl/verilog
13 cosmetic update unneback 4987d 20h /versatile_library/trunk/rtl/verilog
12 added wishbone comliant modules unneback 4988d 16h /versatile_library/trunk/rtl/verilog
11 async fifo simplex unneback 4989d 07h /versatile_library/trunk/rtl/verilog
10 added dff_ce_clear unneback 4991d 06h /versatile_library/trunk/rtl/verilog
8 added dff_ce_clear unneback 4991d 06h /versatile_library/trunk/rtl/verilog
7 mem update unneback 4991d 07h /versatile_library/trunk/rtl/verilog
6 added library files unneback 5004d 07h /versatile_library/trunk/rtl/verilog
5 memories added unneback 5004d 07h /versatile_library/trunk/rtl/verilog
4 added counters unneback 5008d 11h /versatile_library/trunk/rtl/verilog
3 various updates
counter added		 unneback 5011d 06h /versatile_library/trunk/rtl/verilog
2 initial check-in unneback 5012d 07h /versatile_library/trunk/rtl/verilog

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