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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 32

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Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 4868d 07h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4888d 02h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4888d 03h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4888d 03h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4889d 04h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 4889d 04h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4889d 05h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 4889d 19h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 4891d 03h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 4891d 17h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 4891d 22h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 4892d 19h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 4894d 06h /versatile_library/trunk/rtl/verilog/
17 unneback 4957d 19h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 4964d 03h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 4964d 08h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 4964d 09h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 4965d 05h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 4965d 20h /versatile_library/trunk/rtl/verilog/
10 added dff_ce_clear unneback 4967d 19h /versatile_library/trunk/rtl/verilog/

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