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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 33

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Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 5218d 11h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 5225d 21h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 5245d 16h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 5245d 17h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 5245d 17h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 5246d 18h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 5246d 18h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5246d 19h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 5247d 09h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 5248d 17h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 5249d 07h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 5249d 13h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 5250d 09h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 5251d 20h /versatile_library/trunk/rtl/verilog/
17 unneback 5315d 09h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 5321d 17h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 5321d 22h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 5322d 00h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 5322d 20h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 5323d 10h /versatile_library/trunk/rtl/verilog/

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