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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 43

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Rev Log message Author Age Path
43 added logic for parity generation and check unneback 3475d 18h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 3479d 18h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 3479d 19h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 3479d 19h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 3480d 16h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 3480d 17h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 3486d 13h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 3487d 21h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3488d 09h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 3488d 09h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 3501d 11h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 3508d 21h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 3528d 16h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 3528d 16h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 3528d 16h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 3529d 18h /versatile_library/trunk/rtl/verilog/
27 added sync simplex FIFO unneback 3529d 18h /versatile_library/trunk/rtl/verilog/
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3529d 19h /versatile_library/trunk/rtl/verilog/
25 added sync FIFO unneback 3530d 09h /versatile_library/trunk/rtl/verilog/
24 added vl_dff_ce_set unneback 3531d 16h /versatile_library/trunk/rtl/verilog/
23 fixed port map error in async fifo 1r1w unneback 3532d 07h /versatile_library/trunk/rtl/verilog/
22 added binary counters unneback 3532d 12h /versatile_library/trunk/rtl/verilog/
21 reg -> wire in and or mux in logic unneback 3533d 08h /versatile_library/trunk/rtl/verilog/
18 naming convention vl_ unneback 3534d 19h /versatile_library/trunk/rtl/verilog/
17 unneback 3598d 09h /versatile_library/trunk/rtl/verilog/
15 added delay line unneback 3604d 16h /versatile_library/trunk/rtl/verilog/
14 reg -> wire for various signals unneback 3604d 22h /versatile_library/trunk/rtl/verilog/
13 cosmetic update unneback 3604d 23h /versatile_library/trunk/rtl/verilog/
12 added wishbone comliant modules unneback 3605d 19h /versatile_library/trunk/rtl/verilog/
11 async fifo simplex unneback 3606d 10h /versatile_library/trunk/rtl/verilog/

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