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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 4211d 07h /versatile_library/trunk/rtl/verilog/
46 updated parity unneback 4307d 11h /versatile_library/trunk/rtl/verilog/
45 updated timing in io models unneback 4309d 05h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 4312d 05h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4316d 08h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 4320d 08h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 4320d 10h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 4320d 10h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 4321d 07h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 4321d 07h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 4327d 04h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 4328d 12h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4328d 23h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4328d 23h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4342d 01h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4349d 11h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4369d 07h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4369d 07h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4369d 07h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4370d 08h /versatile_library/trunk/rtl/verilog/

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