OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 48

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
48 wb updated unneback 4656d 19h /versatile_library/trunk/rtl/verilog/
46 updated parity unneback 4753d 00h /versatile_library/trunk/rtl/verilog/
45 updated timing in io models unneback 4754d 18h /versatile_library/trunk/rtl/verilog/
44 added target independet IO functionns unneback 4757d 18h /versatile_library/trunk/rtl/verilog/
43 added logic for parity generation and check unneback 4761d 21h /versatile_library/trunk/rtl/verilog/
42 updated mux_andor unneback 4765d 21h /versatile_library/trunk/rtl/verilog/
41 typo in registers.v unneback 4765d 23h /versatile_library/trunk/rtl/verilog/
40 new build environment with custom.v added as a result file unneback 4765d 23h /versatile_library/trunk/rtl/verilog/
39 added simple port prio based wb arbiter unneback 4766d 20h /versatile_library/trunk/rtl/verilog/
38 updated andor mux unneback 4766d 20h /versatile_library/trunk/rtl/verilog/
37 corrected polynom with length 20 unneback 4772d 16h /versatile_library/trunk/rtl/verilog/
36 added generic andor_mux unneback 4774d 01h /versatile_library/trunk/rtl/verilog/
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 4774d 12h /versatile_library/trunk/rtl/verilog/
34 added vl_mux2_andor and vl_mux3_andor unneback 4774d 12h /versatile_library/trunk/rtl/verilog/
33 updated wb3wb3_bridge unneback 4787d 14h /versatile_library/trunk/rtl/verilog/
32 added vl_pll for ALTERA (cycloneIII) unneback 4795d 00h /versatile_library/trunk/rtl/verilog/
31 sync FIFO updated unneback 4814d 19h /versatile_library/trunk/rtl/verilog/
30 updated counter for level1 and level2 function unneback 4814d 20h /versatile_library/trunk/rtl/verilog/
29 updated counter for level1 and level2 function unneback 4814d 20h /versatile_library/trunk/rtl/verilog/
28 added sync simplex FIFO unneback 4815d 21h /versatile_library/trunk/rtl/verilog/

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.