URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 64

Rev	Log message	Author	Age	Path
43	added logic for parity generation and check	unneback	4826d 23h	/versatile_library/trunk/rtl/verilog/
42	updated mux_andor	unneback	4830d 23h	/versatile_library/trunk/rtl/verilog/
41	typo in registers.v	unneback	4831d 00h	/versatile_library/trunk/rtl/verilog/
40	new build environment with custom.v added as a result file	unneback	4831d 01h	/versatile_library/trunk/rtl/verilog/
39	added simple port prio based wb arbiter	unneback	4831d 22h	/versatile_library/trunk/rtl/verilog/
38	updated andor mux	unneback	4831d 22h	/versatile_library/trunk/rtl/verilog/
37	corrected polynom with length 20	unneback	4837d 18h	/versatile_library/trunk/rtl/verilog/
36	added generic andor_mux	unneback	4839d 03h	/versatile_library/trunk/rtl/verilog/
35	added vl_mux2_andor and vl_mux3_andor localparam	unneback	4839d 14h	/versatile_library/trunk/rtl/verilog/
34	added vl_mux2_andor and vl_mux3_andor	unneback	4839d 14h	/versatile_library/trunk/rtl/verilog/