URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] - Rev 67

Rev	Log message	Author	Age	Path
46	updated parity	unneback	4839d 16h	/versatile_library/trunk/rtl/verilog
45	updated timing in io models	unneback	4841d 11h	/versatile_library/trunk/rtl/verilog
44	added target independet IO functionns	unneback	4844d 10h	/versatile_library/trunk/rtl/verilog
43	added logic for parity generation and check	unneback	4848d 14h	/versatile_library/trunk/rtl/verilog
42	updated mux_andor	unneback	4852d 13h	/versatile_library/trunk/rtl/verilog
41	typo in registers.v	unneback	4852d 15h	/versatile_library/trunk/rtl/verilog
40	new build environment with custom.v added as a result file	unneback	4852d 15h	/versatile_library/trunk/rtl/verilog
39	added simple port prio based wb arbiter	unneback	4853d 12h	/versatile_library/trunk/rtl/verilog
38	updated andor mux	unneback	4853d 12h	/versatile_library/trunk/rtl/verilog
37	corrected polynom with length 20	unneback	4859d 09h	/versatile_library/trunk/rtl/verilog