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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 139

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Rev Log message Author Age Path
139 unneback 3616d 12h /versatile_library/trunk/rtl/verilog/Makefile
75 added wb to avalon bridge unneback 3710d 22h /versatile_library/trunk/rtl/verilog/Makefile
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3759d 16h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 3899d 15h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 3907d 20h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 3929d 11h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 3956d 17h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3957d 19h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 3958d 09h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 3960d 13h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 3962d 20h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 4033d 20h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 4049d 11h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 4053d 15h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 4056d 10h /versatile_library/trunk/rtl/verilog/Makefile

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