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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [Makefile] - Rev 62

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Rev Log message Author Age Path
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4019d 18h /versatile_library/trunk/rtl/verilog/Makefile
44 added target independet IO functionns unneback 4159d 18h /versatile_library/trunk/rtl/verilog/Makefile
40 new build environment with custom.v added as a result file unneback 4167d 22h /versatile_library/trunk/rtl/verilog/Makefile
33 updated wb3wb3_bridge unneback 4189d 14h /versatile_library/trunk/rtl/verilog/Makefile
29 updated counter for level1 and level2 function unneback 4216d 19h /versatile_library/trunk/rtl/verilog/Makefile
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4217d 22h /versatile_library/trunk/rtl/verilog/Makefile
25 added sync FIFO unneback 4218d 11h /versatile_library/trunk/rtl/verilog/Makefile
22 added binary counters unneback 4220d 15h /versatile_library/trunk/rtl/verilog/Makefile
18 naming convention vl_ unneback 4222d 22h /versatile_library/trunk/rtl/verilog/Makefile
12 added wishbone comliant modules unneback 4293d 22h /versatile_library/trunk/rtl/verilog/Makefile
5 memories added unneback 4309d 14h /versatile_library/trunk/rtl/verilog/Makefile
4 added counters unneback 4313d 17h /versatile_library/trunk/rtl/verilog/Makefile
3 various updates
counter added
unneback 4316d 12h /versatile_library/trunk/rtl/verilog/Makefile

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