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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 139

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Rev Log message Author Age Path
139 unneback 4538d 21h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
48 wb updated unneback 4721d 01h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
40 new build environment with custom.v added as a result file unneback 4830d 04h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
33 updated wb3wb3_bridge unneback 4851d 19h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4859d 05h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
21 reg -> wire in and or mux in logic unneback 4883d 17h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 4885d 04h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 4948d 17h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 4975d 23h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 4978d 18h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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