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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 22

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 3635d 21h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 3637d 08h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 3700d 21h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 3728d 03h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 3730d 22h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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