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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 33

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Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 4405d 17h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4413d 03h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
21 reg -> wire in and or mux in logic unneback 4437d 14h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 4439d 01h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 4502d 15h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 4529d 20h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 4532d 16h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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