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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [clk_and_reset.v] - Rev 95

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Rev Log message Author Age Path
48 wb updated unneback 3852d 16h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
40 new build environment with custom.v added as a result file unneback 3961d 20h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
33 updated wb3wb3_bridge unneback 3983d 11h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3990d 21h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
21 reg -> wire in and or mux in logic unneback 4015d 09h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
18 naming convention vl_ unneback 4016d 20h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
17 unneback 4080d 09h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
4 added counters unneback 4107d 15h /versatile_library/trunk/rtl/verilog/clk_and_reset.v
3 various updates
counter added
unneback 4110d 10h /versatile_library/trunk/rtl/verilog/clk_and_reset.v

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