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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 100

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100 added cache mem with pipelined B4 behaviour unneback 4667d 09h /versatile_library/trunk/rtl/verilog/defines.v
98 work in progress unneback 4671d 08h /versatile_library/trunk/rtl/verilog/defines.v
97 cache is work in progress unneback 4672d 23h /versatile_library/trunk/rtl/verilog/defines.v
94 clock domain crossing unneback 4678d 01h /versatile_library/trunk/rtl/verilog/defines.v
92 wb b3 dpram with testcase unneback 4678d 09h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 4681d 10h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 4685d 10h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 4685d 10h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4732d 08h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 4732d 08h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4734d 03h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 4735d 04h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 4766d 10h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 4773d 04h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 4874d 03h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 4878d 06h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 4882d 06h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 4882d 08h /versatile_library/trunk/rtl/verilog/defines.v

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