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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [defines.v] - Rev 92

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92 wb b3 dpram with testcase unneback 3106d 10h /versatile_library/trunk/rtl/verilog/defines.v
83 new BE_RAM unneback 3109d 12h /versatile_library/trunk/rtl/verilog/defines.v
76 dependency for wb3 to avalon bus unneback 3113d 11h /versatile_library/trunk/rtl/verilog/defines.v
75 added wb to avalon bridge unneback 3113d 11h /versatile_library/trunk/rtl/verilog/defines.v
62 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3160d 09h /versatile_library/trunk/rtl/verilog/defines.v
61 WB_B3_RAM_BE updates, bte port map + define dependency unneback 3160d 10h /versatile_library/trunk/rtl/verilog/defines.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3162d 05h /versatile_library/trunk/rtl/verilog/defines.v
59 added WB RAM B3 with byte enable unneback 3163d 05h /versatile_library/trunk/rtl/verilog/defines.v
49 added WB_B4RAM with byte enable unneback 3194d 12h /versatile_library/trunk/rtl/verilog/defines.v
48 wb updated unneback 3201d 06h /versatile_library/trunk/rtl/verilog/defines.v
44 added target independet IO functionns unneback 3302d 04h /versatile_library/trunk/rtl/verilog/defines.v
43 added logic for parity generation and check unneback 3306d 07h /versatile_library/trunk/rtl/verilog/defines.v
42 updated mux_andor unneback 3310d 07h /versatile_library/trunk/rtl/verilog/defines.v
40 new build environment with custom.v added as a result file unneback 3310d 09h /versatile_library/trunk/rtl/verilog/defines.v

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