OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [logic.v] - Rev 153

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
46 updated parity unneback 3193d 01h /versatile_library/trunk/rtl/verilog/logic.v
44 added target independet IO functionns unneback 3197d 19h /versatile_library/trunk/rtl/verilog/logic.v
43 added logic for parity generation and check unneback 3201d 23h /versatile_library/trunk/rtl/verilog/logic.v
42 updated mux_andor unneback 3205d 22h /versatile_library/trunk/rtl/verilog/logic.v
40 new build environment with custom.v added as a result file unneback 3206d 00h /versatile_library/trunk/rtl/verilog/logic.v
38 updated andor mux unneback 3206d 21h /versatile_library/trunk/rtl/verilog/logic.v
36 added generic andor_mux unneback 3214d 02h /versatile_library/trunk/rtl/verilog/logic.v
35 added vl_mux2_andor and vl_mux3_andor localparam unneback 3214d 13h /versatile_library/trunk/rtl/verilog/logic.v
34 added vl_mux2_andor and vl_mux3_andor unneback 3214d 13h /versatile_library/trunk/rtl/verilog/logic.v
32 added vl_pll for ALTERA (cycloneIII) unneback 3235d 01h /versatile_library/trunk/rtl/verilog/logic.v

powered by: WebSVN 2.1.0

© copyright 1999-2019 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.