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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 144

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Rev Log message Author Age Path
83 new BE_RAM unneback 3556d 03h /versatile_library/trunk/rtl/verilog/memories.v
77 bridge update unneback 3559d 23h /versatile_library/trunk/rtl/verilog/memories.v
75 added wb to avalon bridge unneback 3560d 03h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 3568d 01h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 3568d 01h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 3568d 01h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 3607d 00h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3608d 20h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 3647d 21h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3757d 01h /versatile_library/trunk/rtl/verilog/memories.v

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