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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 145

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Rev Log message Author Age Path
84 wb ram unneback 3919d 20h /versatile_library/trunk/rtl/verilog/memories.v
83 new BE_RAM unneback 3920d 07h /versatile_library/trunk/rtl/verilog/memories.v
77 bridge update unneback 3924d 04h /versatile_library/trunk/rtl/verilog/memories.v
75 added wb to avalon bridge unneback 3924d 07h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 3932d 05h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 3932d 05h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 3932d 05h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 3971d 05h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3973d 01h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 4012d 01h /versatile_library/trunk/rtl/verilog/memories.v

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