URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 21

Rev	Log message	Author	Age	Path
21	reg -> wire in and or mux in logic	unneback	4884d 05h	/versatile_library/trunk/rtl/verilog/memories.v
18	naming convention vl_	unneback	4885d 16h	/versatile_library/trunk/rtl/verilog/memories.v
14	reg -> wire for various signals	unneback	4955d 18h	/versatile_library/trunk/rtl/verilog/memories.v
11	async fifo simplex	unneback	4957d 06h	/versatile_library/trunk/rtl/verilog/memories.v
7	mem update	unneback	4959d 06h	/versatile_library/trunk/rtl/verilog/memories.v
5	memories added	unneback	4972d 07h	/versatile_library/trunk/rtl/verilog/memories.v