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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 21

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Rev Log message Author Age Path
21 reg -> wire in and or mux in logic unneback 4009d 10h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4010d 21h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4080d 23h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4082d 12h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4084d 11h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4097d 12h /versatile_library/trunk/rtl/verilog/memories.v

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