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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 22

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21 reg -> wire in and or mux in logic unneback 3641d 02h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3642d 13h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3712d 15h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3714d 03h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3716d 03h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3729d 04h /versatile_library/trunk/rtl/verilog/memories.v

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