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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 23

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23 fixed port map error in async fifo 1r1w unneback 4905d 07h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4906d 09h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4907d 20h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4977d 22h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4979d 10h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4981d 10h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4994d 11h /versatile_library/trunk/rtl/verilog/memories.v

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