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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 40

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Rev Log message Author Age Path
40 new build environment with custom.v added as a result file unneback 3519d 15h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3568d 11h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 3569d 13h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3569d 13h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3569d 14h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3570d 04h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3572d 02h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3573d 03h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3574d 14h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3644d 17h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3646d 05h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3648d 05h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3661d 06h /versatile_library/trunk/rtl/verilog/memories.v

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