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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 48

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Rev Log message Author Age Path
48 wb updated unneback 3369d 02h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3478d 06h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3527d 02h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 3528d 04h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3528d 04h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3528d 05h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3528d 19h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3530d 17h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3531d 18h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3533d 05h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3603d 08h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3604d 20h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3606d 20h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3619d 21h /versatile_library/trunk/rtl/verilog/memories.v

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