OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 48

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
48 wb updated unneback 3841d 14h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3950d 17h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3999d 14h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4000d 15h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4000d 15h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4000d 17h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 4001d 06h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 4003d 05h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4004d 06h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4005d 17h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4075d 19h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4077d 08h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4079d 07h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4092d 08h /versatile_library/trunk/rtl/verilog/memories.v

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.