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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 65

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Rev Log message Author Age Path
65 RAM_BE system verilog version unneback 3811d 04h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3813d 00h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 3852d 01h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3961d 04h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 4010d 01h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 4011d 02h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 4011d 02h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 4011d 04h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 4011d 17h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 4013d 16h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 4014d 17h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 4016d 04h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 4086d 06h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 4087d 19h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 4089d 18h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 4102d 19h /versatile_library/trunk/rtl/verilog/memories.v

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