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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 65

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65 RAM_BE system verilog version unneback 3442d 23h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3444d 19h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 3483d 20h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3592d 23h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3641d 20h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 3642d 21h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3642d 21h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3642d 23h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3643d 12h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3645d 10h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3646d 12h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3647d 23h /versatile_library/trunk/rtl/verilog/memories.v
14 reg -> wire for various signals unneback 3718d 01h /versatile_library/trunk/rtl/verilog/memories.v
11 async fifo simplex unneback 3719d 14h /versatile_library/trunk/rtl/verilog/memories.v
7 mem update unneback 3721d 13h /versatile_library/trunk/rtl/verilog/memories.v
5 memories added unneback 3734d 14h /versatile_library/trunk/rtl/verilog/memories.v

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