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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 85

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Rev Log message Author Age Path
85 wb ram unneback 4775d 08h /versatile_library/trunk/rtl/verilog/memories.v
84 wb ram unneback 4775d 09h /versatile_library/trunk/rtl/verilog/memories.v
83 new BE_RAM unneback 4775d 20h /versatile_library/trunk/rtl/verilog/memories.v
77 bridge update unneback 4779d 16h /versatile_library/trunk/rtl/verilog/memories.v
75 added wb to avalon bridge unneback 4779d 20h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 4787d 17h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 4787d 17h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 4787d 18h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 4826d 17h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4828d 13h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 4867d 14h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 4976d 17h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 5025d 14h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 5026d 15h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 5026d 15h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 5026d 17h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 5027d 06h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 5029d 05h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 5030d 06h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 5031d 17h /versatile_library/trunk/rtl/verilog/memories.v

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