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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [memories.v] - Rev 85

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Rev Log message Author Age Path
85 wb ram unneback 3274d 11h /versatile_library/trunk/rtl/verilog/memories.v
84 wb ram unneback 3274d 11h /versatile_library/trunk/rtl/verilog/memories.v
83 new BE_RAM unneback 3274d 22h /versatile_library/trunk/rtl/verilog/memories.v
77 bridge update unneback 3278d 18h /versatile_library/trunk/rtl/verilog/memories.v
75 added wb to avalon bridge unneback 3278d 22h /versatile_library/trunk/rtl/verilog/memories.v
73 no arbiter in wb_b3_ram_be unneback 3286d 20h /versatile_library/trunk/rtl/verilog/memories.v
72 no arbiter in wb_b3_ram_be unneback 3286d 20h /versatile_library/trunk/rtl/verilog/memories.v
68 ram_be updated to optional mem_size unneback 3286d 20h /versatile_library/trunk/rtl/verilog/memories.v
65 RAM_BE system verilog version unneback 3325d 19h /versatile_library/trunk/rtl/verilog/memories.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3327d 15h /versatile_library/trunk/rtl/verilog/memories.v
48 wb updated unneback 3366d 16h /versatile_library/trunk/rtl/verilog/memories.v
40 new build environment with custom.v added as a result file unneback 3475d 20h /versatile_library/trunk/rtl/verilog/memories.v
31 sync FIFO updated unneback 3524d 16h /versatile_library/trunk/rtl/verilog/memories.v
28 added sync simplex FIFO unneback 3525d 18h /versatile_library/trunk/rtl/verilog/memories.v
27 added sync simplex FIFO unneback 3525d 18h /versatile_library/trunk/rtl/verilog/memories.v
26 typo in sync FIFO, added cnt_lfsr_ce_q cnt_lfsr_ce_clear_q unneback 3525d 19h /versatile_library/trunk/rtl/verilog/memories.v
25 added sync FIFO unneback 3526d 09h /versatile_library/trunk/rtl/verilog/memories.v
23 fixed port map error in async fifo 1r1w unneback 3528d 07h /versatile_library/trunk/rtl/verilog/memories.v
21 reg -> wire in and or mux in logic unneback 3529d 08h /versatile_library/trunk/rtl/verilog/memories.v
18 naming convention vl_ unneback 3530d 19h /versatile_library/trunk/rtl/verilog/memories.v

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