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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

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139 unneback 3625d 08h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 3692d 15h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3701d 17h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3705d 15h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3707d 07h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3712d 08h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3719d 18h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3766d 15h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3768d 11h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3807d 12h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3916d 15h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3916d 15h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3965d 12h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3968d 12h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3971d 15h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4035d 04h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4041d 12h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4045d 05h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4045d 05h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4058d 06h /versatile_library/trunk/rtl/verilog/registers.v

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