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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

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139 unneback 4535d 16h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 4603d 00h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 4612d 01h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4616d 00h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4617d 16h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4622d 17h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4630d 02h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4677d 00h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4678d 20h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4717d 20h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4827d 00h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4827d 00h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4875d 21h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4878d 21h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4882d 00h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4945d 13h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4951d 21h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4955d 13h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4955d 13h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4968d 15h /versatile_library/trunk/rtl/verilog/registers.v

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