OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

Rev

Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 unneback 3188d 09h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 3255d 17h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3264d 18h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3268d 17h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3270d 09h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3275d 10h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3282d 19h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3329d 17h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3331d 12h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3370d 13h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3479d 16h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3479d 17h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3528d 14h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3531d 13h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3534d 17h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 3598d 06h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 3604d 14h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 3608d 06h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 3608d 06h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 3621d 08h /versatile_library/trunk/rtl/verilog/registers.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.