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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 100

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Rev Log message Author Age Path
100 added cache mem with pipelined B4 behaviour unneback 4638d 18h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4642d 17h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4644d 08h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4649d 09h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4656d 19h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4703d 16h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4705d 12h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4744d 13h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4853d 16h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4853d 16h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4902d 13h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4905d 13h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4908d 16h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4972d 06h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4978d 13h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4982d 06h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4982d 06h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4995d 08h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 5002d 07h /versatile_library/trunk/rtl/verilog/registers.v

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