OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 112

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
100 added cache mem with pipelined B4 behaviour unneback 3258d 13h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3262d 11h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3264d 03h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3269d 04h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3276d 14h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3323d 11h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3325d 07h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3364d 08h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3473d 11h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3473d 11h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3522d 08h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3525d 08h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3528d 11h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 3592d 00h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 3598d 08h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 3602d 01h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 3602d 01h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 3615d 02h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 3622d 01h /versatile_library/trunk/rtl/verilog/registers.v

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.