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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 139

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139 unneback 4596d 05h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 4663d 13h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 4672d 14h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 4676d 13h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 4678d 04h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 4683d 05h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4690d 15h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4737d 13h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4739d 08h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4778d 09h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4887d 12h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4887d 13h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4936d 09h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4939d 09h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4942d 12h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5006d 02h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5012d 09h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5016d 02h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5016d 02h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5029d 04h /versatile_library/trunk/rtl/verilog/registers.v

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