OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 148

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
139 unneback 3711d 02h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 3778d 10h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3787d 11h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3791d 10h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3793d 02h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3798d 03h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3805d 12h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3852d 10h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3854d 06h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3893d 06h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4002d 10h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4002d 10h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4051d 07h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4054d 07h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4057d 10h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4120d 23h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4127d 07h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4130d 23h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4130d 23h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4144d 01h /versatile_library/trunk/rtl/verilog/registers.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2022 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.