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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 152

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139 unneback 3876d 17h /versatile_library/trunk/rtl/verilog/registers.v
116 syncronizer clock unneback 3944d 01h /versatile_library/trunk/rtl/verilog/registers.v
100 added cache mem with pipelined B4 behaviour unneback 3953d 02h /versatile_library/trunk/rtl/verilog/registers.v
98 work in progress unneback 3957d 01h /versatile_library/trunk/rtl/verilog/registers.v
97 cache is work in progress unneback 3958d 17h /versatile_library/trunk/rtl/verilog/registers.v
94 clock domain crossing unneback 3963d 18h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 3971d 03h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4018d 01h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4019d 21h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4058d 22h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 4168d 01h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 4168d 01h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 4216d 22h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 4219d 22h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 4223d 01h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 4286d 14h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 4292d 22h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 4296d 15h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 4296d 15h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 4309d 16h /versatile_library/trunk/rtl/verilog/registers.v

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