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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 75

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75 added wb to avalon bridge unneback 3075d 02h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 3121d 23h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 3123d 19h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 3162d 20h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 3271d 23h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 3271d 23h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 3320d 20h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 3323d 20h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 3326d 23h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 3390d 13h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 3396d 20h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 3400d 13h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 3400d 13h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 3413d 15h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 3420d 14h /versatile_library/trunk/rtl/verilog/registers.v

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