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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [registers.v] - Rev 94

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Rev Log message Author Age Path
94 clock domain crossing unneback 4798d 03h /versatile_library/trunk/rtl/verilog/registers.v
75 added wb to avalon bridge unneback 4805d 12h /versatile_library/trunk/rtl/verilog/registers.v
64 SPR reset value unneback 4852d 10h /versatile_library/trunk/rtl/verilog/registers.v
60 added wb b3 byte enable memory, added test in makefile through icarus, typo in latch fixed unneback 4854d 06h /versatile_library/trunk/rtl/verilog/registers.v
48 wb updated unneback 4893d 06h /versatile_library/trunk/rtl/verilog/registers.v
41 typo in registers.v unneback 5002d 10h /versatile_library/trunk/rtl/verilog/registers.v
40 new build environment with custom.v added as a result file unneback 5002d 10h /versatile_library/trunk/rtl/verilog/registers.v
29 updated counter for level1 and level2 function unneback 5051d 07h /versatile_library/trunk/rtl/verilog/registers.v
24 added vl_dff_ce_set unneback 5054d 07h /versatile_library/trunk/rtl/verilog/registers.v
18 naming convention vl_ unneback 5057d 10h /versatile_library/trunk/rtl/verilog/registers.v
17 unneback 5120d 23h /versatile_library/trunk/rtl/verilog/registers.v
15 added delay line unneback 5127d 07h /versatile_library/trunk/rtl/verilog/registers.v
10 added dff_ce_clear unneback 5130d 23h /versatile_library/trunk/rtl/verilog/registers.v
8 added dff_ce_clear unneback 5130d 23h /versatile_library/trunk/rtl/verilog/registers.v
5 memories added unneback 5144d 01h /versatile_library/trunk/rtl/verilog/registers.v
3 various updates
counter added
unneback 5151d 00h /versatile_library/trunk/rtl/verilog/registers.v

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