URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 23

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	4884d 06h	/versatile_library/trunk/rtl/verilog/versatile_library.v
22	added binary counters	unneback	4884d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v
21	reg -> wire in and or mux in logic	unneback	4885d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
18	naming convention vl_	unneback	4886d 19h	/versatile_library/trunk/rtl/verilog/versatile_library.v
17		unneback	4950d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
15	added delay line	unneback	4956d 16h	/versatile_library/trunk/rtl/verilog/versatile_library.v
14	reg -> wire for various signals	unneback	4956d 21h	/versatile_library/trunk/rtl/verilog/versatile_library.v
13	cosmetic update	unneback	4956d 22h	/versatile_library/trunk/rtl/verilog/versatile_library.v
12	added wishbone comliant modules	unneback	4957d 18h	/versatile_library/trunk/rtl/verilog/versatile_library.v
11	async fifo simplex	unneback	4958d 09h	/versatile_library/trunk/rtl/verilog/versatile_library.v
10	added dff_ce_clear	unneback	4960d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
8	added dff_ce_clear	unneback	4960d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
7	mem update	unneback	4960d 09h	/versatile_library/trunk/rtl/verilog/versatile_library.v
6	added library files	unneback	4973d 10h	/versatile_library/trunk/rtl/verilog/versatile_library.v