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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 23

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Rev Log message Author Age Path
23 fixed port map error in async fifo 1r1w unneback 4012d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4012d 23h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4013d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4015d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4078d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4085d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4085d 09h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4085d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4086d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4086d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4088d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 4088d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 4088d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 4101d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v

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