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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 24

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Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 4006d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4007d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4007d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4008d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4010d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4073d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4079d 22h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4080d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4080d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4081d 01h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4081d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4083d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 4083d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 4083d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 4096d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v

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