OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 24

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
24 added vl_dff_ce_set unneback 3498d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 3498d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 3498d 20h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 3499d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 3501d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 3564d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 3571d 00h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 3571d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 3571d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 3572d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 3572d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 3574d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 3574d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
7 mem update unneback 3574d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
6 added library files unneback 3587d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v

powered by: WebSVN 2.1.0

© copyright 1999-2020 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.