OpenCores
URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 32

Rev

Go to most recent revision | Details | Compare with Previous | Blame

Filtering Options

Clear current filter

Rev Log message Author Age Path
32 added vl_pll for ALTERA (cycloneIII) unneback 3984d 16h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4004d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4004d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4004d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4005d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4005d 13h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4006d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4007d 11h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4008d 02h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4008d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4009d 03h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4010d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4074d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4080d 12h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4080d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4080d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4081d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4082d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4084d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v
8 added dff_ce_clear unneback 4084d 04h /versatile_library/trunk/rtl/verilog/versatile_library.v

1 2 Next >

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2021 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.