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[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 33

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Rev Log message Author Age Path
33 updated wb3wb3_bridge unneback 4864d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
32 added vl_pll for ALTERA (cycloneIII) unneback 4871d 18h /versatile_library/trunk/rtl/verilog/versatile_library.v
31 sync FIFO updated unneback 4891d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
30 updated counter for level1 and level2 function unneback 4891d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
29 updated counter for level1 and level2 function unneback 4891d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
28 added sync simplex FIFO unneback 4892d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
27 added sync simplex FIFO unneback 4892d 15h /versatile_library/trunk/rtl/verilog/versatile_library.v
25 added sync FIFO unneback 4893d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
24 added vl_dff_ce_set unneback 4894d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
23 fixed port map error in async fifo 1r1w unneback 4895d 05h /versatile_library/trunk/rtl/verilog/versatile_library.v
22 added binary counters unneback 4895d 10h /versatile_library/trunk/rtl/verilog/versatile_library.v
21 reg -> wire in and or mux in logic unneback 4896d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
18 naming convention vl_ unneback 4897d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
17 unneback 4961d 06h /versatile_library/trunk/rtl/verilog/versatile_library.v
15 added delay line unneback 4967d 14h /versatile_library/trunk/rtl/verilog/versatile_library.v
14 reg -> wire for various signals unneback 4967d 19h /versatile_library/trunk/rtl/verilog/versatile_library.v
13 cosmetic update unneback 4967d 21h /versatile_library/trunk/rtl/verilog/versatile_library.v
12 added wishbone comliant modules unneback 4968d 17h /versatile_library/trunk/rtl/verilog/versatile_library.v
11 async fifo simplex unneback 4969d 08h /versatile_library/trunk/rtl/verilog/versatile_library.v
10 added dff_ce_clear unneback 4971d 07h /versatile_library/trunk/rtl/verilog/versatile_library.v

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