URL https://opencores.org/ocsvn/versatile_library/versatile_library/trunk

Subversion Repositories versatile_library

[/] [versatile_library/] [trunk/] [rtl/] [verilog/] [versatile_library.v] - Rev 44

Rev	Log message	Author	Age	Path
23	fixed port map error in async fifo 1r1w	unneback	5030d 22h	/versatile_library/trunk/rtl/verilog/versatile_library.v
22	added binary counters	unneback	5031d 03h	/versatile_library/trunk/rtl/verilog/versatile_library.v
21	reg -> wire in and or mux in logic	unneback	5032d 00h	/versatile_library/trunk/rtl/verilog/versatile_library.v
18	naming convention vl_	unneback	5033d 11h	/versatile_library/trunk/rtl/verilog/versatile_library.v
17		unneback	5097d 00h	/versatile_library/trunk/rtl/verilog/versatile_library.v
15	added delay line	unneback	5103d 08h	/versatile_library/trunk/rtl/verilog/versatile_library.v
14	reg -> wire for various signals	unneback	5103d 13h	/versatile_library/trunk/rtl/verilog/versatile_library.v
13	cosmetic update	unneback	5103d 14h	/versatile_library/trunk/rtl/verilog/versatile_library.v
12	added wishbone comliant modules	unneback	5104d 10h	/versatile_library/trunk/rtl/verilog/versatile_library.v
11	async fifo simplex	unneback	5105d 01h	/versatile_library/trunk/rtl/verilog/versatile_library.v